CMOS is, and will continue to be ... this is that the entire device is normally designed as a single synchronous circuit. By using asynchronous logic many of these problems can be resolved.

The Rambus Compute Express Link® (CXL®) 3.1 controller is a parameterizable design for ASIC and FPGA implementations. It leverages the Rambus PCIe® 6.1 controller architecture for the CXL.io ...